David Kanter published his Bulldozer article at Real World Technologies, with many details you won't find anywhere else.
Anandtech published a Sandy Bridge preview of a CPU model with the top bin integrated GPU (containing 12 EUs).
The lower modules seem to look more like an original layout. The likely 2M L2 caches and L3 cache blocks have a significant area difference. So they might have been scaled during the photoshopping or use different SRAM macro cells. I'll come back to that later.
A recently published paper (with some relation to AMD) describes the effect of workload phase prediction in frequency boost techniques. You can download it here. It shows the potential of knowing in advance, when performance will be needed and where.