A lot happened during the last week, including some rumors about the begin of production of different Bulldozer based CPUs. I read it all day after day and always felt the need to blog about this. This was not possible due to several reasons. For such cases I'll change my strategy somewhat, as you'll see below. Now let's get back to the rumors. So does Charlie of SemiAccurate reports about Orochi (server die to be used for Interlagos and Valencia), which might be demoed at the Financial Analyst Day 2010. Further he writes about samples and production dates, also in relation to Llano's dates, where we heard at the last CC, that it will hit the market before Bulldozer.
XbitLabs instead reports that desktop Bulldozer chips (Zambezi) will see start of production in April 2011. Further they (actually Anton Shilov) report about Llano's start of production in July. The problem with these dates is, that first AMD officially said, that Llano will come before Bulldozer and second that comments by John Fruehe indicate, that this is far from reality and we should better wait for new information to be given at the Financial Analyst Day.
Although it's rather unlikely that we'll hear about Orochi die sizes this week. But already several people including me analyzed the photoshopped die photo and found it to be in the ballpark of 300 sqmm (+/-20) in size. My analysis based on L2 cell size, I/O cell size (as Hans de Vries did) and L1 I$ size relations also resulted in a module area of ~17-19 sqmm and a L2 area of a little more than 10 sqmm. So this estimation lands at roughly 28 sqmm for a module with cache. Take this with a grain of salt.
There will soon be another blog from John, covering instruction set extensions in Bulldozer (ver 1 I suppose). It might cover LWP, AES-NI or some previously unsupported SSE extension. The new instructions for "Bulldozer 2" as found on the gcc mailing list (I reported) already made it into the news. Just a few days earlier the "what if" outlook became the topic of another news story.
A blog by AMD's Elsie Wahlig features a video, where she's explaining the Bulldozer topology in some detail to help software developers make better use of the new structure found in those processors based on Bulldozer microarchitecture.
What we still don't know and what is topic of an ongoing discussion at P3DNow! (sneak peek in German) is the clocking structure of Bulldozer. So far the clock speeds have been discussed, and also the advanced turbo boost mode. But nothing much has been read in regard of differently clocked parts in a module. There is research with links to AMD, as I also mentioned on comp.arch. Stay tuned.
Because of the reasons I mentioned above, I decided to start my own twitter feed "Dresdenboy". If I find something worth sharing, I'll do it there first.
P.S.: Some fun in relation to processors: "Bulldozer" logos from K-9 for dog harnesses.