Before finding the time to do any deeper analysis of how the facts which were presented at ISSCC 2011 last week I decided to let you at least know the current state of die size analysis. So far The Reg published an apparently unphotoshopped die photo last week. Taking this one and doing some pixel count measurements resulted in a die size of ~294 mm˛ for the Orochi die, which will be used for Zambezi, Valencia and Interlagos processors (obviously two of them for the latter). This is in line with measurements by Hans de Vries (292 mm˛) and also my earlier estimation of 300 +/- 20 mm˛. Hiroshige Goto just published his article on Bulldozer (translated) with an even larger version of the die photo.
In the following picture (a little bit resized) you can see, how I counted:
Some preliminary clock frequency number for Interlagos
Two weeks ago I looked for some info on supercomputers and found some upgrade plans, which included some Interlagos details:
Significant Upgrade in June 2011 – 232 AMD 2.3 GHz 16-core OpteronInterlagosprocessors – 3,712 compute cores, 116 32-core nodes – 7.4 TB DDR3 memory, 64 GB/node, 2.0 GB/core
In June 2011, a 720-teraflop Cray XE6 system will be added to Gaea. It will employ the next-generation AMD Interlagos 16-core processor. After the installation of that second system, the original 260-teraflop system will be upgraded with the same AMD Interlagos processor to achieve 386 teraflops.
So it looks like there will be Interlagos model running at 2.3 GHz base clock frequency. If this is any indication and given that super computer chips often are not running at the top bin frequencies, there might be Interlagos models up to 2.5 or even 2.6 GHz
And here is a bunch of links, which I will sort later:
A fresh video of swapping two Magny Cours processors for Interlagos processors:
News regarding Bulldozer capable AM3 boards:
Update: This round of news turned out to be based on wrong interpretations, possibly even some facts lost in translation, see John Fruehe's comment on this and the updates in the articles linked above.
John Fruehe's long explaination of how a Bulldozer could and could not compared to two cores of Magny Cours and that hypothetical single cored Bulldozer module:
AMD blogs with some info about the ISSCC presentations:
More ISSCC related links:
A little bit of info about Bulldozer's 256b AVX performance compared to it's 128b AVX performance (no absolute numbers), as found in a recent GCC patch:
Attached is the patch to force gcc to generate 128-bit avx instructions for bdver1. We found that for the current Bulldozer processors, AVX128 performs better than AVX256. For example, AVX128 is 3% faster than AVX256 on CFP2006, and 2~3% faster than AVX256 on polyhedron.